1. Field of the Invention
The present invention relates to buffer circuits and, more particularly, to full-swing buffer circuits with a NMOS pull-up transistor. Still more particularly, the present invention relates to full-swing buffer circuits with a NMOS pull-up transistor and a charge pump.
2. Description of the Prior Art
An output buffer is conventionally adapted to buffer data processed by a semiconductor integrated circuit. More specifically, the output buffer receives a signal and generates an output signal with a sufficient voltage level to drive external peripheral circuits. A typical output buffer usually includes a pull-up driver for generating a logic high level output signal having a voltage level approximately equal to the supply voltage (e.g., Vdd), and a pull-down driver for generating a logic low level output signal having a voltage approximately equal to ground potential (i.e., V.sub.ss). In order to achieve full-swing output, the pull-up driver usually uses a p-channel metal-oxide-semiconductor (PMOS) transistor as a pull-up device and a n-channel metal-oxide-semiconductor (NMOS) transistor as a pull-down device. More specifically, the PMOS pull-up device is connected to have its source coupled to receive the supply voltage and its drain connected to the output lead of the output buffer, whereas the NMOS pull-down device has its source connected to receive ground potential and its drain connected to the output lead of the output buffer. When the output buffer is to generate a logic high level output signal, the PMOS pull-up device is turned on and the NMOS pull-down device is turned off, thereby electrically connecting the output lead of the output buffer to the supply voltage source. Thus, the output buffer generates a logic high level output signal having a voltage approximately equal to the supply voltage. Conversely, when the output buffer is to generate a logic low level output signal, the NMOS pull-down device is turned on and the PMOS pull-up device is turned off. Consequently, the output buffer generates a logic low level output signal having a voltage approximately equal to ground potential.
However, a problem can arise when the output buffer is part of an integrated circuit having its substrate backbiased. The substrate of the integrated circuit is commonly biased at -1.5 volts in order to reduce the leakage current, for example, in a dynamic random access memory (DRAM). As a result of this backbiasing of the substrate, the PMOS pull-up transistor is susceptible to the well-known latch-up phenomenon.
One solution to this problem is to use a NMOS pull-up transistor instead of a PMOS pull-up transistor. A control signal received at the gate of the NMOS pull-up transistor causes the NMOS transistor to turn on or off. This control signal causes the NMOS transistor to turn on and pull-up the voltage at the output buffer's output lead to generate a logic high level output signal. In this conventional buffer, this control signal has a maximum voltage limited to the supply voltage, which only allows the NMOS device to pull-up the voltage at the output buffer's output lead to approximately the supply voltage minus the threshold voltage of the NMOS device (e.g., Vdd-Vt). More specifically, increasing the output signal voltage beyond the supply voltage minus the threshold voltage causes the gate-to-source voltage of the NMOS device to be less than the threshold voltage, thereby turning the NMOS device off. Thus, a conventional NMOS pull-up driver circuit does not achieve a full-swing output signal voltage. Accordingly, there is a need for a full-swing output buffer that is not susceptible to latch-up.